With the increasing demand for electronic devices to have reduced current consumption and to avoid the use of off-chip components there has been an increasing trend for electronic devices to perform processing in the digital domain.
Consequently, there has been an increasing demand for high resolution, low power, and inexpensive analog to digital converters ADC.
One type of ADC that is commonly used for analog to digital conversion is the over sampling ADC based upon sigma delta Σ Δ modulation. Over sampling ADC's use an over sampling ratio OSR that is the ratio of the sampling frequency of the sigma delta modulator to twice the bandwidth (Nyquist frequency) of the input signal. The over sampling ratio will be greater than one and will often be greater than a few tens. For conventional n-th order sigma delta modulators SDM, the signal to quantization noise ratio increases by n*6 dB+3 dB for each doubling of the OSR. Thus, better resolution is achieved by implementing a higher OSR.
The SDM is a multi-order modulator that is arranged to provide noise shaping, such that the quantization noise is small in the frequency band of interest and large elsewhere.
For applications that operate with a low bandwidth, for example 20 kHz, a simple SDM, for example a 2nd order SDM, would be suitable for providing the required noise shaping.
However, more recently there has been a need to use ADC's in high bandwidth applications, such as cellular systems and wireless local area networks WLAN. Where, for example, a WCDMA handset can be required to operate with a bandwidth of the order of 2 MHz. For a low order SDM to provide the required analog to digital conversion for a high bandwidth signal, with the required noise shaping, a high OSR would be required that would not only be difficult to design but would also result in a high power consumption for the SDM.
However, it is possible for a SDM to provide the required noise shaping characteristics for high bandwidth applications with a reduced OSR by increasing the order of the SDM.
However, for the SDM to have the dynamic range required for high bandwidth applications it is desirable for the SDM to include or to be combined with an embedded parallel (i.e. flash) ADC having a 2 or more bit quantizer. However, the use of a high bit flash ADC can result in high power consumption. For example, the power dissipation for a 6 bit quantizer can correspond to approximately a quarter of the total SDM power dissipation.
It is desirable to improve this situation.